(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming interconnects in a semiconductor substrate by using an improved damascene process.
(2) Description of the Related Art
With the advent of very and ultra large scale integration (VLSI and ULSI) circuits, the number of interconnections in a semiconductor substrate has increased astronomically. The interconnections are made between passive and active devices within the substrate, as well as between a multitude of wiring layers that constitute the circuits on the substrate. Damascene is a process which simplifies the forming of interconnections in a semiconductor substrate.
In the single damascene process, grooves are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, the conductive hole openings are also formed in the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers.
In contrast, conventionally, the metal layers and the interconnecting layers are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate.
In the standard dual damascene process the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via opening and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with another resist material which is exposed to a second mask with image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive line in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal.
Although this standard dual damascene offers advantages over other conventional processes for forming interconnections, it has a number of disadvantages, such as the edges of the via openings in the lower half of the insulating layer are poorly defined because of the two etchings and the via edges being unprotected during the second etching, as described by Avanzino, et al., in U.S. Pat. No. 5,686,354.
Avanzino uses a thin via mask in forming the via openings in order to protect the edges from irregularities. Thus, following Avanzino, a portion of an interconnection structure (1) shown in FIG. 1a, is coated with a layer (40) of commercially available resist and with a conductive line pattern (45) as shown in FIGS. 1b and 1c. Resist layer (40) is coated on the surface (33) of an insulating layer (30), which is usually an oxide of about 1 micrometer (.mu.m) thick. Layer (30) is shown to have a lower portion (30a) and an upper portion (30b) in FIG. 1a in order to facilitate the description of the steps of this conventional process.
The resist is a positive resist and the undeveloped resist (40) serves as an etch mask for etching a conductive line opening (45') in the uncovered surface (33) of the insulating layer. The conductive line opening and a subsequent via opening, when filled with a conductive material, will provide an interconnection to a conductive line (20) in an underlying insulating layer (10). As illustrated in FIG. 1b, the insulating layer at the uncovered surface (33) is anisotropically etched with a plasma gas(es), such as carbon tetrafluoride (CF.sub.4), in a commercially available etcher, such as a parallel plate reactive ion etch (RIE) apparatus or, alternatively, an electron cyclotron resonance (ECR) plasma reactor to replicate the mask pattern in the upper portion (30b) and thereby create the conductive line opening (45) in layer (30). Resist layer (40) serves as an etch barrier during etching, which is timed for a predetermined depth, which is usually half the thickness of insulating layer (30). A negative resist, in place of the positive resist, can also be used with the mask pattern being reversed.
After resist layer (40) is removed by a conventional technique such as ashing in an oxygen (O.sub.2) plasma, a thin conformal etch barrier layer (50) is deposited on the surface (33) of the insulating layer and walls (35) and bottom (37) of the conductive line opening (45) as shown in FIG. 1c. Conventional etch barriers, or etch-stops are silicon nitride (Si.sub.3 N.sub.4, SiN), silicon oxynitride (SiO.sub.x N.sub.y), and titanium nitride (TiN). The etch properties of the etch barrier are such that it is or exhibits selectivity to the etchant, such as carbon tetrafluoride (CF.sub.4) containing fluorine atoms for the SiO.sub.2.
As shown in FIG. 1d, a second coating of positive resist (60) is applied as a thick layer on the etch barrier layer (50). A via pattern (65') is formed in resist layer (60) in alignment with the conductive line opening (45), as shown in FIGS. 1e and 1f. The undeveloped resist (60) serves as an etch mask for anisotropically etching an opening (67) in the etch-stop layer (50) which in turn is used as a mask in etching via hole (65) into lower portion (30a) as shown in FIG. 1g. That is, Avanzino, et al., teach the removal of thick resist mask (60) prior to the etching, although could remain during the etching of the via hole. This is because, a thin mask, such as the thin, about 1000 .ANG. TiN thick etch barrier layer (50) provides more precise edges for etching via opening (65) in contrast to a thick mask. Barrier layer (50) remains in the openings in filling the conductive line opening (45) and via opening (65) with a conductive material (70) such as aluminum copper. Substrate (1) is then subjected to chemical mechanical polishing, thus forming a flat, planarized surface (73) and a composite metal interconnection (75) of the dual damascene structure shown in FIG. 1f.
In another U.S. Pat. No. 5,614,765, Avanzino, et al., disclose a method of forming self aligned via dual damascene using only one mask pattern for the formation of both the conductive lines and vias. A different method of forming conductive lines, or wires, for a semiconductor device is disclosed in U.S. Pat. No. 5,604,156. Huang, et al., teach a the forming of an interconnection structure having a reduced interwiring spacing by a modified dual damascene process.
While prior art has addressed some of the disadvantages and problems associated with standard dual damascene process as described above, the present invention addresses still another problem, namely, the problem of damage caused to a substrate surface, such as silicon, when that surface is unprotected and exposed to multiple etching energy while dual forming of the conductive line and hole openings of the dual damascene structure.